A Low Power FinFET Charge Pump for Energy Harvesting Applications

A FinFET Charge Pump is proposed for low power energy harvesting applications. It is designed to pump a 150mV power supply, generated from an energy harvester, to a regulated 650mV, while supplying 1uA of load current, with a 20mV voltage ripple in steady state (SS) operation. At these conditions, the systems power consumption is 4.85uW and is 31.76% efficient. Under no loading conditions, the charge pump reaches SS operation in 50us, giving it the fastest rise time of the compared state of the art efforts mentioned in this work. The minimum power supply voltage for the system to function is 93mV where it gives a regulated output voltage of 425mV.


I. INTRODUCTION
The IoT (Internet of Things) paradigm is expected to have a pervasive impact in the next years. The ubiquitous character of IoT nodes implies that they must be untethered and energy autonomous [1]. Every energy harvesting system has a power management circuit to convert the scavenged energy to a more usable power supply. Typically, designers use switched inductor or switched capacitor (SC) techniques to achieve this goal. "The SC voltage multiplier is becoming one of the most critical Integrated Circuit (IC) blocks for energy harvesting in wireless sensor nodes to generate a voltage high enough for microwatt sensing and computing ICs in a nanometer complementary metal-oxide-semiconductor (CMOS) from environmental energy sources such as mechanical vibration, electromagnetic wave, and temperature gradient" [2]. A Charge Pump (CP) is a SC circuit that is heavily utilized in energy harvesting and memory circuit design to create multiple on-chip supply voltages. Most CPs use large and expensive capacitors that lead to larger chip areas, higher power consumption and potentially, off chip components.
It is expected that by the end of 2020 there will be 50 billion devices connected to IoT [3]. With this in mind, any efforts to improve CP performance can directly contribute to some of the most popular industries in today's day and age. Some of the important design constraints for energy harvesting CP systems include minimum area, short rise time, high output current, high power efficiency and smallest possible operating voltage. Adiabatic design strategies are commonly used to improve CP performance. One adiabatic design strategy is to implement efficient gate controlling methods, such as the ones seen in [4] and [5]. This work also aims to take advantage of the inherent characteristics of FinFET (Field Effect Transistor) devices to provide better performance at low supply voltages. Even though FinFETs have been prominent in industry for quite some time, very few research efforts have applied FinFET devices to CP design. After extensive research, the only other similar FinFET CP discovered is shown in [6]. In this work a FinFET Charge Pump with adiabatic gate control is designed for low power energy harvesting applications to convert a 150mV power supply to a 633mV pumped output voltage at a load current I L = 1µA without the use of large capacitors or off-chip components.

II. FINFET CHARACTERISTICS
The FinFET devices used in this work are from the ASAP7 7nm Process Design Kit (PDK) that was developed by Arizona State University in partnership with ARM Ltd. to be used for academic purposes. This is a realistic PDK based on the assumptions for the 7nm technology node and is not tied to any foundry [7].
The ASAP7 PDK has 4 different transistor flavors, the two that are utilized in this work are the low threshold voltage (LVT) and super low threshold voltage (SLVT). I-V characteristics of the LVT and SLVT devices, each with 3 fins, are presented in Fig. 1, which represents the device currents up to a V DD of 150mV . SLVT devices are distinguished by an extra red line in the gate of the device and are primarily used in the CP unit core schematic. At a 1V power supply the FinFET is 18% faster than the planar MOSFET, however, at a 0.7V power supply, the FinFET is 37% faster than its planar cousin [8].

A. Block Diagram
The top level block representation of the proposed design is shown in Fig. 2 and shows an energy harvester providing the power supply, V DD , which creates a clock that is distributed to each unit CP and outputs a pumped supply voltage, V DDP . V DDP is then converted to a level that the existing logic will be able to sense its level and control the feedback signals pwrup and pwrdown. When V DDP is below the desired level, pwrup goes high and chooses the faster clock frequency. Then, when V DDP is close to 700mv, pwrdown deactivates pass gates so that no clocking signals can get to the pump cores. The DC load current then turns on at 50µs to act as the load to the pump.

A. Optimum Clock Frequency
The optimum clock frequency was selected by substituting an ideal source for the clock and sweeping its parameters. 4M Hz was chosen as it seemed to be a relative maximum. The power efficiency, η, is defined as the ratio of the output power to the input power and is shown in Eq. (1).
Where V DDP is the pumped output voltage, and I DDP is the pumped output current. V DD and I DD are the chip supply voltage and current.

B. Mux Controlled Oscillator
A mux controlled oscillator (MCO) was designed to provide the clocking scheme for this system. The MCO in Fig, 3 resembles a standard voltage controlled oscillator (VCO), however, the operation is different. The oscillating frequency f is calculated by Eq. (2) where I s is the current flowing through the branch, C osc is the total capacitance attached to the node joining the inverter stages, N is the number of stages.
From Eq. (2), C osc , N and I s were determined to be 8f F , 5 and 48nA respectively to give 4M Hz. The signal pwrup then Fig. 3. MCO Schematic selects the number of stages that the signal will propagate through and changes the frequency. When pwrup is high, f is 4M Hz, and when low, f is 2M Hz. This clock is then sent to a standard non-overlapping clock generator to create CLKA and CLKB which are then driven to the individual CP cores.

V. CHARGE PUMP UNIT CELL
The CP unit cell that is used in this design is similar to the ones used in [4], [9], [5] and [10]. To make sure that the CP can operate in low voltage applications the CTS and levelshifters (LS) are replaced with SLVT devices. The schematic for the unit cell is shown in Fig. 4 with the accompanying waveforms to help illustrate the operation of this circuit. The Fig. 4. Charge Pump Unit Core Schematic reason this CP topology is often implemented in low voltage applications is that each level shifter (LS) controls the gate signal of accompanying CTS by utilizing a two-time step charge sharing strategy developed in [11]. This strategy is illustrated by the G3 waveform in Figure 4. This strategy allows CTS3 to take advantage of the fact that there is still charge on the capacitor from the previous stage, where the first time voltage step of G3 will initiate charge sharing between the capacitors of the two stages. This leads to a 50% reduction of the energy that is delivered by the source because the first half is coming from charge sharing.

VI. VDDP SENSING
The V DDP Sensing block takes vddp sense, max sense, CLKA and CLKB as inputs and generates the pwrup and pwrdown signals used to control the pumping of the cores. The main sub-blocks are the clocked comparator, beta multiplier reference, integrator, input buffer and the DC average generator. The block level schematic is shown in Fig. 5 where the output is fed back to the clock and pump divers respectively. Fig. 6 shows the progression of how pwrup is created

A. Pumped Output Voltage
The transient for the pumped output voltage, V DDP at an I L of 1µA and a V DD of 150mV is shown in Fig. 7 where it can be seen that the design constraints for the system were reasonably met. I L is switched on during the transient simulation at 50µs to show the rise time of V DDP and to show the functionality of the feedback loop where the maximum voltage doesn't go above 700mV as this is the maximum V DD for the FinFETs. To find the minimum V DD that this system can operate at, the power supply was swept first by 10mV increments from 0mV to 150mV where a noticeable jump occurred between 90mV and 100mV . Another sweep was then performed in increments of 2mV from 91mV to 99mV where the minimum power supply voltage is found to be a very competitive 93mV . This is shown in Fig. 8 where the more important simulations are solid lines to highlight the obvious switching point as well as those relative to the output with the 150mV V DD being the design constraint.  Table I. It is important to mention that the results presented in this work are simulation only and could change based on completing the layout for this design. Some advantages of this work as compared to the others presented in Table II, include the fastest rise time, no off-chip components, can provide 633mV at 1µA of load current while being able to function at the second smallest V DD of 93mV . Some of the disadvantages of this work include the largest output voltage ripple and the lowest efficiency of 31.76% where the 2nd lowest of the compared works is 38.8%. Of the designs presented with no off-chip components, this work can handle 4 times the amount of load current as the next highest. A. Comparison Table   TABLE II